An Implementation of the Behavioral Verilog Simulator in Ptolemy

Modeling and simulation of digital hardware at the behavioral level enable designers to experiment with a system without specifying implementation details. Verilog is a language that supports modeling and simulation at di erent levels of abstraction. However, all components in the same design must conform to a certain timing model, which may not be natural for all components. Ptolemy is a simulation environment for systems with heterogeneous timing models. This report describes the incorporation of the behavioral Verilog simulator into Ptolemy by a compiler, which expresses the simulation semantics of Verilog in C++.